1. Field of the Invention
This invention relates to a horizontal synchronizing signal generating circuit which, based upon an externally applied horizontal synchronizing reference signal, produces and outputs an internal horizontal synchronizing reference signal.
Further, the invention relates to a circuit, and to a synchronizing method, for generating an internal synchronizing signal, which is synchronized to a given external synchronizing signal, by utilizing a PLL (phase-locked loop) which includes an edge detecting-type digital phase comparator.
2. Description of the Related Art
As shown in FIGS. 1 and 2, a circuit for producing an internal horizontal synchronizing reference signal and an internal vertical synchronizing reference signal, which are based upon and synchronized to an externally applied horizontal synchronizing reference signal and an externally applied vertical synchronizing reference signal, and for performing synchronous control based upon the produced internal horizontal and vertical synchronizing reference signals, is used in the subordinate synchronizing signal generator of a system having two, namely a main and a subordinate, synchronizing signal generators (SSG).
In FIG. 1, a main synchronizing signal generator 10 has a reference oscillator 11 which generates a reference clock signal (having a frequency of, e.g., 28 MHz). On the basis of the reference clock signal, the main synchronizing signal generator 10 produces and outputs such signals as a horizontal synchronizing reference signal HD.sub.0 and a vertical synchronizing reference signal VD.sub.0 for interlaced scanning, and a synchronizing pulse CP for color separation. The horizontal and vertical synchronizing reference signals HD.sub.0, VD.sub.0 are applied to a subordinate synchronizing signal generator 20A as external horizontal and vertical synchronizing reference signals, respectively. The synchronizing pulse CP is applied to a color-separation synchronizing signal generator 12, which produces a synchronizing signal for color separation.
The subordinate synchronizing signal generator 20A incorporates the above-mentioned synchronous control circuit, which includes a PLL (a phase-locked loop) circuit 21. Using a clock signal generated by the PLL circuit 21, the synchronous control circuit produces internal horizontal and vertical synchronizing signals based upon and synchronized to the external horizontal and vertical synchronizing reference signals HD.sub.0, VD.sub.0 provided by the main synchronizing signal generator 10. Further, based upon these internal horizontal and vertical synchronizing signals, the subordinate synchronizing signal generator 20A produces and outputs horizontal and vertical drive signals .phi.H and .phi.V for a CCD (charge-coupled device) 22 used as an image pick-up device, and a sampling signal CDS of a read signal from the CCD 22.
In FIG. 2, the external horizontal and vertical synchronizing reference signals HD.sub.0, VD.sub.0 are applied to a subordinate synchronizing signal generator 20B from the main synchronizing signal generator 10 along with a clock signal (having a frequency of, e.g., 14 MHz) obtained by frequency-dividing the reference clock signal. Since the subordinate synchronizing signal generator 20B is supplied with the clock signal, this subordinate synchronizing signal generator 20B need not have a PLL circuit. Using the clock signal inputted thereto, the subordinate synchronizing signal generator 20B produces internal horizontal and vertical synchronizing reference signals synchronized to the external horizontal and vertical synchronizing reference signals HD.sub.0, VD.sub.0, respectively, produces a composite synchronizing signal C.SYNC from these signals and outputs the composite synchronizing signal. The main synchronizing signal generator 10 in FIG. 2 produces the horizontal and vertical drive signals .phi.H and .phi.V for the CCD 22.
The systems shown in FIGS. 1 or 2 are applied to systems in which a camera head (the portion which includes the image pick-up device of a still-video camera or a video camera) is separated from a main unit which internally incorporates circuitry (inclusive of a white-balance control circuit, a gamma-correction circuit, a matrix circuit and an encoder, etc.) for processing a video signal picked up by the camera head, by way of example. When the system shown in FIG. 1 is applied, the camera head is provided with the subordinate synchronizing signal generator 20A, and the video-signal processing circuitry is provided with the main synchronizing signal generator 10. The systems shown in FIG. 1 and 2 are further applied to systems including comprising a recorder for recording a video signal as picked up by a still-video camera or a video camera on a recording medium, and a playback device connected to the recorder. If the system illustrated in FIG. 2 were applied to such a system, the recorder would be provided with the main synchronizing signal generator 10 and the playback device would be provided with the subordinate synchronizing signal generator 20B. In such case, the external horizontal and vertical synchronizing reference signals HD.sub.0, VD.sub.0 could be applied to the subordinate synchronizing signal generator 20B separate from the video signal, or they could be superimposed on the video signal, in which case synchronous separation would be performed by the subordinate synchronizing signal generator 20B. The system shown in FIG. 1 is suitable for a case where the two generators 10, 20A are situated comparatively far apart, while the system shown in FIG. 2 is suitable for a case where the two generators 10, 20B are situated comparatively close together.
To facilitate an understanding of the art, the discussion will be limited to the horizontal synchronizing reference signal. The subordinate synchronizing signal generators 20A, 20B shown in FIGS. 1 and 2 each have a horizontal reset circuit for synchronizing the internal horizontal synchronizing reference signal, which is produced using the clock signal generated by the PLL circuit 21 or the externally applied clock signal, to the external horizontal synchronizing reference signal. Basically, when the internal horizontal synchronizing reference signal produced becomes de-synchronized, the horizontal reset circuit resets the circuit, which produces the internal horizontal synchronizing reference signal, at a predetermined timing of the external horizontal synchronizing reference signal, and forcibly synchronizes the internal horizontal synchronizing reference signal, which is outputted by this circuit, to the external horizontal synchronizing reference signal.
In the case where the main synchronizing signal generator 10 and subordinate synchronizing signal generator 20B use a common clock signal, as illustrated in FIG. 2, a phase difference, which conforms to the transmission rate of the clock signal, develops between the clock signal used by the main synchronizing signal generator 10 and the clock signal used by the subordinate synchronizing signal generator 20B. In order to prevent jitter from being produced by this phase difference between the clock signals used by the two generators 10, 20B, the conventional practice is to provide the horizontal reset circuit with a narrow dead zone whose width is on the order of .+-.1 period of the clock signal. If the de-synchronization between the internal synchronizing reference signal and the external synchronizing reference signal is within .+-.1 clock period, the resetting operation is not carried out. In other words, resetting is performed only when the de-synchronization is greater than .+-.1 clock period.
However, the concept of providing the aforesaid narrow dead zone cannot be employed in the subordinate synchronizing signal generator 20A having the internal PLL circuit 21 shown in FIG. 1. The reason is as follows: The PLL circuit detects a phase difference between the external horizontal synchronizing reference signal and the internal horizontal synchronizing reference signal, and controls the oscillation frequency of a voltage-controlled oscillator, which produces the clock signal dependent upon the phase difference detected. In the narrow dead zone mentioned above, resetting is performed at all times, a correct phase comparison cannot be executed in the PLL circuit and an appropriate value cannot be obtained for the oscillator frequency of the voltage-controlled oscillator. Though an arrangement can be conceived in which the reset operation is not performed at all, this would lengthen the transient response time of the PLL circuit until the PLL circuit is stabilized and correct synchronization is achieved.
An example of a system which requires a circuit for generating an internal synchronizing signal synchronized to external synchronizing signal is the aforementioned image pick-up system having the separate camera head. The camera head of a video camera or a still-video camera has an internal solid-state electronic image pick-up device such as a CCD. The image pick-up device outputs a video signal representing the subject whose image has been picked up. This video signal is sent to a signal processing unit situated at a location remote from the camera head. As mentioned earlier, the signal processing unit internally incorporates processing circuitry, such as the white-balance control circuit, gamma-correction circuit, matrix circuit and encoder, as well as a circuit for generating the synchronizing signals (horizontal and vertical synchronizing signals) used by these circuits. In order to synchronize the operation of the signal processing unit and the operation of the camera head, such as an operation for reading a signal charge from the CCD, the synchronizing signal from the signal processing unit is applied to the camera head as an external synchronizing signal. As shown in FIG. 3, the camera head is provided with a synchronizing signal generating circuit which generates an internal synchronizing signal that is synchronized to an external synchronizing signal.
FIG. 3 illustrates a circuit for generating an internal horizontal synchronizing reference signal HD.sub.i that is synchronized to an external horizontal synchronizing reference signal HD.sub.0. This circuit includes a PLL circuit, which is constituted by a phase comparator 61, a low-pass filter 62, a voltage-controlled oscillator 63 and a circuit 64 for producing a horizontal synchronizing reference signal.
The voltage-controlled oscillator 63 generates a clock signal whose center frequency is a high frequency of 14.318 MHz. The clock signal is applied to the circuit 64, which produces the horizontal synchronizing reference signal, and is used in other synchronous control.
The circuit 64 for producing the horizontal synchronizing reference signal includes a frequency divider, logical circuitry, etc., and is adapted to output the internal horizontal synchronizing reference signal HD.sub.i obtained by frequency-dividing the clock signal (by about 910, for example). When the internal horizontal synchronizing reference signal HD.sub.i and the external horizontal synchronizing reference signal HD.sub.0 are out of synchronization (for example, when the leading edges of the two horizontal synchronizing reference signals HD.sub.i, HD.sub.0 are spaced apart by more than a predetermined phase), a reset signal synchronized to the leading edge of the external horizontal synchronizing reference signal HD.sub.0 is applied to the circuit 64 for producing the horizontal synchronizing reference signal. As a result, the circuit 64 is reset and generates the internal horizontal synchronizing reference signal HD.sub.i having a leading edge synchronized to the reset signal. Therefore, the internal horizontal synchronizing reference signal HD.sub.i is synchronized to the external horizontal synchronizing reference signal HD.sub.0.
The phase comparator 61 is an edge-detecting type digital phase comparator which compares the phases of the external horizontal synchronizing reference signal HD.sub.0 provided by the signal processing unit and the internal horizontal synchronizing reference signal HD.sub.i outputted by the circuit 64, and generates an output representing the result of the comparison. The output of the phase comparator 61 is applied as a control voltage to the voltage controlled oscillator 63 via the low-pass filter 62, which is of the charge-pump type and includes a capacitor. The oscillation frequency of the voltage-controlled oscillator 63 varies in conformity with the control voltage applied thereto.
FIG. 4 shows the control voltage/oscillation frequency characteristic of the voltage-controlled oscillator 63. With an increase in the control voltage, the oscillation frequency also increases in proportion. The oscillation frequency of the voltage-controlled oscillator 63 varies by following up the inputted control voltage over a range from a minimum frequency f.sub.min to a maximum frequency f.sub.max.
FIG. 5 illustrates an example of the construction of a leading-edge detecting digital phase comparator for the phase comparator 61.
As shown in FIG. 5, the phase comparator includes a flip-flop 71 for detecting the leading edge of the external horizontal synchronizing reference signal HD.sub.0, a flip-flop 72 for latching the result of the detection operation, a flip-flop 73 for detecting the leading edge of the internal horizontal synchronizing reference signal HD.sub.i, a flip-flop 74 for latching the result of the detection operation, an AND gate 75 for forcibly resetting the flip-flops 71, 72 and forcibly setting the flip-flops 73, 74, a p-channel FET 76 turned on by an output Q of the flip-flop 71, and an n-channel FET 77 turned on by an output Q of the flip-flop 73. The FETs 76, 77 are serially connected between an operating voltage V.sub.DD and ground, and the junction between them leads to an output terminal of the phase comparator.
FIGS. 6a and 6b illustrate the operation of the above-described internal horizontal synchronizing reference signal generating circuit (FIGS. 3 and 5).
FIG. 6a illustrates a case where the oscillation frequency of the voltage-controlled oscillator 63 is relatively high (higher than the frequency of the clock signal for producing the external horizontal synchronizing reference signal HD.sub.0) and the leading edge of the internal horizontal synchronizing reference signal HD.sub.i is produced earlier than the leading edge of the external horizontal synchronizing reference signal HD.sub.0.
In response to the leading edge of the internal horizontal synchronizing reference signal HD.sub.i, the flip-flop 73 is reset, so that the n-channel FET 77 is turned on by the output Q of the flop-flop. As a result, the output of the phase comparator 61 falls from a high-impedance (Hi-Z) level to the L level. When the leading edge of the external horizontal synchronizing reference signal HD.sub.0 subsequently appears, the flip-flop 73 is forcibly set, and therefore the n-channel FET 77 returns to the off state. The output voltage of the low-pass filter 62 falls as a result of the output of the phase comparator 61 temporarily assuming the L level (namely for a period of time corresponding to the phase difference between the two signals HD.sub.i and HD.sub.0). The output voltage of the filter 62 is applied to the voltage-controlled oscillator 63, which possesses the control-voltage/oscillation-frequency characteristic shown in FIG. 4. As a result, the oscillation frequency of the voltage-controlled oscillator 63 declines in response to the decline in the output voltage of low-pass filter 62. Accordingly, the PLL circuit operates in a direction which reduces the phase difference between the two horizontal synchronizing reference signals HD.sub.0, HD.sub.i, so that the internal horizontal synchronizing reference signal HD.sub.i is synchronized to the external horizontal synchronizing reference signal HD.sub.0.
FIG. 6b illustrates a case where the oscillation frequency of the voltage-controlled oscillator 63 is relatively low and the leading edge of the external horizontal synchronizing reference signal HD.sub.0 occurs earlier than the leading edge of the internal horizontal synchronizing reference signal HD.sub.i (namely a case where the phase difference resides outside the limits of a dead zone in which resetting is forbidden). In FIG. 6b, the reset operation which actually takes place is indicated by the solid line; the dashed line indicates the operation that would take place if a second reset signal were not applied to the circuit 64 which produces the horizontal synchronizing reference signal.
The operation indicated by the dashed line will be described first.
In response to the leading edge of the external horizontal synchronizing reference signal HD.sub.0, the flip-flop 71 is set, so that the p-channel FET 76 is turned on by the output Q of this flip-flop 71. As a result, the output of the phase comparator 61 rises from the high-impedance level to the H level. When the leading edge of the internal horizontal synchronizing reference signal HD.sub.i subsequently appears, the flip-flop 71 is forcibly reset, and therefore the p-channel FET 76 returns to the off state. The output of the phase comparator 61 temporarily assumes the H level, whereby the output voltage of the low-pass filter 62 rises, the oscillation frequency of the voltage-controlled oscillator 63 increases and the internal horizontal synchronizing reference signal HD.sub.i is synchronized to the external horizontal synchronizing reference signal HD.sub.0.
However, when the phase difference between the signals HD.sub.i and HD.sub.0 is large and falls outside the dead zone, the circuit 64 which produces the horizontal synchronizing reference signal is reset at the timing of the leading edge of the external horizontal synchronizing reference signal HD.sub.0, and the internal horizontal synchronizing reference signal HD.sub.i produced has a leading edge synchronized to the leading edge of the external horizontal synchronizing reference signal HD.sub.0. As a consequence, the output of the phase comparator 61 is held in the high-impedance state and the output of the low-pass filter 62 does not change. In other words, in this case the oscillation frequency of the voltage-controlled oscillator 63 remains permanently unchanged and absolutely no pull-in operation is performed by the PLL circuit.